1. Field of the Invention
The present invention relates to a bipolar RAM (random access memory) apparatus and, more particularly, to a discharge circuit used in a bipolar RAM apparatus for executing fast transition of selected memory cells to a nonselected state.
2. Description of the Prior Art
In a bipolar RAM apparatus, it has been customary heretofore to employ such a circuit configuration as shown in FIG. 1. More specifically, in discharge circuits 2.sub.1 -2.sub.N provided in individual rows of a memory cell array 1, negative logic outputs Y.sub.N1 -Y.sub.NN of decoders 3.sub.1 -3.sub.N are used as driving outputs, which are then delayed by means of delay circuits 4.sub.1 -4.sub.N consisting of resistors R.sub.a1 -R.sub.aN, R.sub.b1 -R.sub.bN and capacitors C.sub.a1 -C.sub.aN. The outputs thus delayed are applied to the bases of discharge transistors Q.sub.c1 -Q.sub.cN respectively to thereby discharge the memory cells for transition of the same to a nonselected state.
However, in such conventional circuit configuration, a total discharge current Idis comes to flow in the drive transistor Q.sub.b of the selected word line, so that the base-emitter voltage V.sub.BE of the transistor Q.sub.b is rendered great to consequently raise a disadvantage of reduction in the noise margin.
Furthermore, as obvious from FIG. 2, a great current Idis required merely during the discharge time is kept flowing steadily to eventually bring about an increased current consumption. Moreover, due to the concentrative flow of such great current Idis in one word line, it becomes necessary to widen the word line against electron migration, hence raising another problem of an increase in both the memory cell area and the wiring capacitance.